1. Field of the Invention
This invention relates generally to digital logic circuits, and, more particularly, to digital logic circuits which receive signals alternating between two different voltage levels.
2. Description of the Related Art
Digital logic circuits typically quantize signal voltage levels to represent two or more logic levels or states. In positive binary logic, a signal voltage level within a voltage range extending downward from a maximum operating voltage typically represents a logic “high” level (e.g., a logic ‘1’ state), and a signal voltage level within a voltage range extending upward from a minimum operating voltage typically represents a logic “low” level (e.g., a logic ‘0’ state).
Electromagnetic events occurring in and around digital logic circuits produce unwanted “noise” signals. These unwanted noise signals may be coupled into nodes or signal lines of digital logic circuits, causing voltage level variations of logic signals on the nodes or signal lines. For this reason, reliable digital logic circuits incorporate “noise margins” (NM) for both the logic high level (NMH) and the logic low level (NML). When a noise signal has an amplitude less than NML, and a logic gate receives a signal at an input representing the logic low level and including the noise signal, the noise signal will be attenuated as the received signal passes from the input to an output of the logic gate. Similarly, when a noise signal has an amplitude less than NMH, and the logic gate receives a signal at an input representing the logic high level an including the noise signal, the noise signal will be attenuated as the received signal passes from the input to an output of the logic gate. As it is equally likely for noise signals to be coupled into signals representing logic low levels and logic high levels, it is desirable that the noise margins NMH and NML be substantially equal.
Power supply conductors used to distribute a “positive” power supply voltage and a reference or “ground” power supply voltage to logic gates of a digital logic circuit have finite electrical resistances and inductances. When the outputs of several of the logic gates change simultaneously, a relatively large switching current “pulse” flows through the power supply conductors. The switching current pulse causes voltage drops across the electrical resistances and inductances of the power supply conductors. As a result, the positive power supply voltage level at the logic gates with changing outputs, and at neighboring logic gates, is momentarily reduced, or “droops.” At the same time, the ground power supply voltage level at the logic gates with changing outputs, and at the neighboring logic gates, is momentarily increased, or “bounces.” Such power supply droop and ground bounce may generate noise signals within the digital logic circuit. If not attenuated by virtue of noise margins NMH and NML, the noise signals may cause the digital logic circuit to produce incorrect output signals.
Dynamic random access memory (DRAM) devices are commonly used to store data (e.g., within computer systems). Modern synchronous DRAM (SDRAM) devices receive an externally generated clock signal, and use the clock signal to synchronize operations with other devices (e.g., an SDRAM controller). Input signal reception and output signal generation are synchronized with voltage level transitions (i.e., edges) of the clock signal. SDRAM devices include multiple “banks” of memory, and performances of SDRAM devices may be increased by interleaving memory accesses among the multiple memory banks in order to hide required signal line precharge times within the SDRAM devices. In addition, input signals received by more conventional DRAM devices determine the functions performed by the DRAM devices. In contrast, input signals received by SDRAM devices represent commands. The commands may be used to program registers within the SDRAM devices which control operations of the SDRAM devices, thus allowing for programmable operation of SDRAM devices.
A clock signal used to synchronize operations of components of a synchronous digital logic circuit (e.g., including an SDRAM device) alternates periodically between a high voltage level and a low voltage level. The high voltage level may be within a voltage range extending downward from a maximum operating voltage representing a logic high level (e.g., a logic ‘1’ state). Correspondingly, the low voltage level may be within a voltage range extending upward from a minimum operating voltage representing a logic “low” level (e.g., a logic ‘0’ state). The operations of the components are typically synchronized to transitions of the clock signal between the high voltage level and the low voltage level (i.e., rising or falling edges of the clock signal). Accordingly, the clock signal must be distributed to the components such that all components “see” the edges of the clock signal at substantially the same time. In the manner described above, finite resistances and inductances of conductors used to distribute clock signals (e.g., clock signal conductors and a ground voltage grid or plane), and/or noise signals coupled into the conductors, may reduce the high voltage level of the clock signal and/or increase the low voltage level of the clock signal.
An input buffer of a component receiving a clock signal (e.g., a logic circuit or a clock signal buffer) typically uses a fixed switching point or “trip point” voltage to produce a “regenerated clock signal.” The switching point voltage is typically set to a value mid way between selected “ideal” high and low voltage levels of the clock signal. The received clock signal voltage is compared to the switching point voltage (e.g., via a comparator). If the clock signal voltage is greater than the switching point voltage, the input buffer may produce the regenerated clock signal within an output voltage range extending downward from the maximum operating voltage and representing the logic high level (e.g., the logic ‘1’ state). On the other hand, if the clock signal voltage is less than the switching point voltage, the input buffer may produce the regenerated clock signal within an output voltage range extending upward from the minimum operating voltage and representing the logic low level (e.g., the logic ‘0’ state).
Practical clock signals transition between the low voltage level and the high voltage level in finite amounts of time (i.e., have finite “rise times”), and similarly transition between the high voltage level and the low voltage level in finite lengths of time (i.e., have finite “fall times”). Characterizing such practical clock signals may involve determining a mid voltage level mid way between the high and low voltage levels, and determining “mid points” of rising and falling edges of the clock signal where the rising and falling edges pass through the mid voltage level. The period of such a practical clock signal may be defined as an amount of time between a mid point of a rising edge of the clock signal and a mid point of the next rising edge of the clock signal. The “duty cycle” of a practical clock signal having finite rise and fall times may be defined as a ratio of an amount of time between a mid point of a rising edge of the clock signal to a mid point of the next falling edge to the period of the clock signal.
Where a high voltage level of a clock signal is decreased by an amount when traversing a clock distribution network (i.e., due to conductor electrical characteristics and/or noise signals), and a low voltage level of the clock signal is increased by the same amount, an input buffer employing the above described method for regenerating the clock signal by comparing the clock signal voltage to a fixed switching point voltage may expectedly produce the regenerated clock signal having the same duty cycle as the received clock signal. However, in situations where the high and low voltage levels of the clock signal are changed by different amounts, and when the high and low voltage levels are both increased or both decreased, the regenerated clock signal produced by the input buffer differs from the duty cycle of the received clock signal. As a result of such changes in duty cycle, the components of the digital logic circuit may not “see” the edges of the clock signal at substantially the same time. When determining a minimum period of the clock signal, such variations in edge transition times must be accounted for such that the period of the clock signal is sufficient to allow the digital logic circuit to produce correct output signals despite the variations in edge transition times.
It would thus be advantageous to have an input buffer circuit having a variable switching point dependent upon actual high and low voltage levels of a received input signal (e.g., a clock signal), and not a fixed switching point established based upon ideal high and low voltage levels of the input signal. In a synchronous digital logic system using a clock signal to synchronize component operations, such an input buffer would reduce variations in edge transition times of the clock signal received by the components, thereby allowing the period of the clock signal to be reduced, and the performance of the synchronous digital logic system to be increased.